1. Field of the Invention
The present invention relates to an image-capturing device.
2. Description of the Related Art
In recent years, as solid-state image-capturing devices, complementary metal oxide semiconductor (CMOS) image sensors have attracted attention and have been put to practical use. While charge coupled device (CCD) image sensors are manufactured using a dedicated manufacturing process, the CMOS image sensors can be manufactured using a general semiconductor manufacturing process. Because of this, the CMOS image sensor can implement multiple functions using various functional circuits embedded therein, for example, as in a system on chip (SOC).
As the image sensor in which the functional circuits are embedded, technology related to a column analog-to digital (AD) conversion type image sensor provided with an AD conversion circuit serving as the functional circuit for every column of the pixel array disposed in a matrix and configured to sequentially output AD-converted digital signals of each row for every column, for example, as shown in Japanese Patent No. 4831146 (hereinafter referred to as Patent Literature 1), is disclosed.
FIG. 5 is a block diagram illustrating a schematic configuration of a conventional solid-state image-capturing device. In FIG. 5, a configuration of the column AD conversion type image sensor disclosed in Patent Literature 1 is simplified and illustrated. The conventional solid-state image-capturing device 900 illustrated in FIG. 5 includes a pixel array unit 10, a vertical scanning circuit 20, a plurality of pixel signal read lines 2, a plurality of AD conversion processing circuits 3, a horizontal scanning circuit 30, a plurality of signal output lines 6, and a plurality of signal output circuits 7.
The pixel array unit 10 is a pixel array in which a plurality of unit pixels 11 are disposed in a matrix. Each of the unit pixels 11 includes a photodiode, and generates a pixel signal (analog signal) corresponding to an intensity of incident light within a given accumulation time.
The vertical scanning circuit 20 performs read control of each unit pixel 11 for every row of the pixel array unit 10 and causes the pixel signal generated by each unit pixel 11 to be output to each pixel signal read line 2 disposed in correspondence with each column of the pixel array unit 10 and commonly connected to all unit pixels 11 of the same column.
Each of the AD conversion processing circuits 3 is connected to one corresponding pixel signal read line 2, that is, disposed in correspondence with one column of the pixel array unit 10. Each AD conversion processing circuit 3 includes an AD conversion unit 4 configured to convert (AD-convert) an input analog signal into a digital signal and a plurality of memory units 5 configured to hold the digital signal obtained by the AD conversion unit 4 performing the AD conversion for every corresponding bit. The AD conversion unit 4 AD-converts a pixel signal input through the corresponding pixel signal read line 2 and outputs a signal (hereinafter referred to as a “bit signal”) of each bit of a digital signal of an AD conversion result to the memory unit 5 corresponding to each bit. Each of the memory units 5 holds the corresponding bit signal output from the AD conversion unit 4.
The horizontal scanning circuit 30 sequentially performs output control of each memory unit 5 provided within the AD conversion processing circuit 3 for every column of the pixel array unit 10, that is, sequentially performs output control for each AD conversion processing circuit 3, and causes the bit signal held by each memory unit 5 provided in the AD conversion processing circuit 3 for performing the output control to be output to each signal output line 6 commonly connected to the same bit of the digital signal.
Each of the signal output circuits 7 is connected to the signal output line 6 of the corresponding bit, and externally outputs the bit signal in which any one corresponding bit is output from one memory unit 5, that is, the bit signal in which any one bit is output from one AD conversion processing circuit 3 to the signal output line 6, as each bit signal of a digital output signal output by the solid-state image-capturing device 900.
Through this configuration, the solid-state image-capturing device 900 sequentially outputs digital signals obtained by the AD conversion processing circuits 3 AD-converting pixel signals output from the unit pixels 11 within the pixel array unit 10 as digital output signals. In the solid-state image-capturing device 900, each component is formed on a single semiconductor substrate.
As illustrated in FIG. 5, in the conventional column AD conversion type image sensor, the AD conversion processing circuit 3 is provided for every column of the pixel array unit 10. Thus, a width (a length in the horizontal direction of each AD conversion processing circuit 3 in FIG. 5) of a region available to form the AD conversion processing circuit 3 disposed in each column within the column AD conversion type image sensor is required to be within an interval (pixel pitch) of the unit pixels 11 provided in the pixel array unit 10, that is, to be within a width (a length of the horizontal direction of one pixel in FIG. 5) of one column when the unit pixel 11 is formed.
Because of this, in the conventional column AD conversion type image sensor, the signal output circuit 7 for outputting a digital output signal of each bit is disposed at a position outside the AD conversion processing circuit 3 disposed on a farthest end (a position of the right of the rightmost AD conversion processing circuit 3 in FIG. 5) as illustrated in FIG. 5.